Quality of oscillators and clocks is commonly characterized in terms of either phase noise or RMS phase jitter.
Phase noise is a measure of the oscillator short term phase instability, observable as frequency spreading about the fundamental tone. The phase noise is specified as a power spectral density function \(L_\phi(f)\), defined as the ratio of the noise power (over \(1Hz\) bandwidth; at an offset frequency from the fundamental tone) to the signal power.
Phase jitter is the deviation of clock period from the ideal periodicity. It is the time domain counterpart of the phase noise. Quantitatively, the phase jitter value corresponds to the area under the phase noise curve (up to a scale factor), and is usually given in seconds or radians.
While the two descriptions are closely related, which to use depends on the context of the case at hand. On a circuit level design, where unmodulated signals are mainly concerned, the use of phase noise is more widespread. On a system level, signals are modulated by random data stream causing the phase noise to smear across the signal bandwidth. It then makes sense to adapt an averaged quantity, such as phase jitter.
This application calculates the phase jitter corresponding to a given phase noise spectral density \(L_\phi(f)\).
Using this application is fairly straightforward and best illustrated with an example.
Suppose it is desired to assess the signal to noise (SNR) degradation due to clock jitter of an analog to digital convertor (ADC). Assume the ADC is driven by an \(100MHz\) clock with a phase noise in the following table.
| Offset (Hz) | Phase Noise (dBc/Hz) |
|---|---|
| 1K | -126 |
| 10K | -128 |
| 100K | -130 |
| 1M | -160 |
| 10M | -163 |
| 50M | -163 |
To find the clock jitter, enter the clock frequency and phase noise, and set the integration limits from \(1KHz\) to \(50MHz\), assuming contribution from outside this bandwidth is negligible. Once finished filling out all the fields, click Calculate to preform the calculation. The RMS Phase Jitter in seconds should equal \(316.0fs\).
The ADC SNR due to clock jitter is given by the relation $$SNR(dBFS) = -20log(2 \pi f_{in} \sigma)$$ where \(f_{in}\) is the ADC input frequency and \(\sigma\) is RMS phase jitter in seconds. Taking for example \(f_{in} = 125 MHz\) with \(\sigma = 316.0fs\) gives ADC SNR of 72.1dBFS.
The application uses the following set of equations to carry the calculation.
The integrated phase noise \(\Delta\phi^2\) equals the area under the curve over the given integration bandwidth, $$\Delta\phi^2 = \int_{f_1}^{f_2} L_\phi(f) df$$ where \(L_\phi(f)\) is the phase noise spectral density in linear scale (\(\frac{1}{Hz}\)), and \(f_1\) and \(f_2\) are the lower and upper integration bound (\(Hz\)).
The phase jitter is than $$RMS \, Phase \, Jitter \, (rad)= \sqrt{2 \Delta \phi^2}$$ $$RMS \, Phase \, Jitter \, (sec)= \frac{\sqrt{2 \Delta \phi^2}}{2 \pi f_0}$$ where \(f_0\) is the oscillator frequency (\(Hz\)).
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