LC Filter Design Tool Description

LC Filter Design Tool is a web-based application for lumped LC filter synthesis. It is feature rich, user-friendly and available for free from any desktop or mobile device.

Features

Contents

1 Introduction

The RF filter is a two-port linear device used to attenuate certain unwanted frequencies of a signal while passing other wanted ones. The frequency band over which the filter passes through is called the passband, and the frequency band it rejects is called the stopband. The filter frequency response is classified according to its passband and stopband boundaries. The most common ones are:

Along having frequency selectivity, the RF filter is expected to have minimal influence on the pass band phase and amplitude response and maintain good impedance match at each port.

Types of Filter Responses

2 S-parameters

The passive RF filter is a linear device with matched ports, which is typically described in the frequency domain; it is therefore convenient to model its response using s-parameters. An overview on s-parameters is available in Wikipedia. In the present context, the passive RF filters s-parameters consists of a two-by-two complex and frequency dependent matrix, \[ \mathbf{S}= \begin{bmatrix} S_{11} & S_{12} \\ S_{21} & S_{22} \end{bmatrix} \]

Filter Two-Port Network Schematics

Because the device is passive (and non-magnetic) it is also reciprocal, meaning \(S_{21} = S_{12}\) and only three parameters are needed to describe the filter response, \(S_{11}\), \(S_{21}\), and \(S_{22}\). The magnitude and phase of these correspond to several frequency dependent measures important for filter analysis:

Parameter Relation
Insertion Loss (dB)\(IL = -20log_{10}(|S_{21}|)\)
Input Return Loss (dB)\(RL_{in} = -20log_{10}(|S_{11}|)\)
Output Return Loss (dB)\(RL_{out} = -20log_{10}(|S_{22}|)\)
Phase (rad)\(\phi = arg(S_{21})\)
Group Delay (sec)\(\tau_{d} = -\frac{1}{2\pi}\frac{d\phi}{df}\)

3 Standard Values

By default, filters are synthesized with exact components values and show ideal frequency response. However, actual mass-produced components have values limited to a set of standard values and bounded below by some minimum; moreover they are subject to manufacturing tolerances and temperature variations. Consequently, when implementing the design, actual component values differ from the nominal values and may negatively impact the filter performances.

To model the filter sensitivity to these variations, the user can limit the capacitance and inductance to E series of preferred values, and also set their minimum values.

Standard Values Settings

3.1 E Series

Each E series values are equally spaced on a logarithmic scale, such that the relative variation/tolerance from the exact value is constant. Below is the list of available E series values and their corresponding tolerances. For more information on E series see Wikipedia.

E6 values (20% tolerance)

1.0, 1.5, 2.2, 3.3, 4.7, 6.8

E12 values (10% tolerance)

1.0, 1.2, 1.5, 1.8, 2.2, 2.7, 3.3, 3.9, 4.7, 5.6, 6.8, 8.2

E24 values (5% tolerance)

1.0, 1.1, 1.2, 1.3, 1.5, 1.6, 1.8, 2.0, 2.2, 2.4, 2.7, 3.0, 3.3, 3.6, 3.9, 4.3, 4.7, 5.1, 5.6, 6.2, 6.8, 7.5, 8.2, 9.1

E48 values (2% tolerance)

1.00, 1.05, 1.10, 1.15, 1.21, 1.27, 1.33, 1.40, 1.47, 1.54, 1.62, 1.69, 1.78, 1.87, 1.96, 2.05, 2.15, 2.26, 2.37, 2.49, 2.61, 2.74, 2.87, 3.01, 3.16, 3.32, 3.48, 3.65, 3.83, 4.02, 4.22, 4.42, 4.64, 4.87, 5.11, 5.36, 5.62, 5.90, 6.19, 6.49, 6.81, 7.15, 7.50, 7.87, 8.25, 8.66, 9.09, 9.53

E96 values (1% tolerance)

1.00, 1.02, 1.05, 1.07, 1.10, 1.13, 1.15, 1.18, 1.21, 1.24, 1.27, 1.30, 1.33, 1.37, 1.40, 1.43, 1.47, 1.50, 1.54, 1.58, 1.62, 1.65, 1.69, 1.74, 1.78, 1.82, 1.87, 1.91, 1.96, 2.00, 2.05, 2.10, 2.15, 2.21, 2.26, 2.32, 2.37, 2.43, 2.49, 2.55, 2.61, 2.67, 2.74, 2.80, 2.87, 2.94, 3.01, 3.09, 3.16, 3.24, 3.32, 3.40, 3.48, 3.57, 3.65, 3.74, 3.83, 3.92, 4.02, 4.12, 4.22, 4.32, 4.42, 4.53, 4.64, 4.75, 4.87, 4.99, 5.11, 5.23, 5.36, 5.49, 5.62, 5.76, 5.90, 6.04, 6.19, 6.34, 6.49, 6.65, 6.81, 6.98, 7.15, 7.32, 7.50, 7.68, 7.87, 8.06, 8.25, 8.45, 8.66, 8.87, 9.09, 9.31, 9.53, 9.76

4 Export

Exporting a filter enables the user to easily:

4.1 LTSpice

LTSpice is a free circuit simulation software by Analog Devices. It runs natively on Windows and macOS, and also works well on Linux using the Wine compatibility layer. The latest version is available for download on analog.com.

4.1.1 LTSpice Simulation Settings

The export dialog will create an LTSpice .asc file which includes the filter schematics as well as auto-generated simulation settings. The user can select the type of simulation to preform, either being S-parameters or transient response. On top of that, each simulation can be run with finite Q inductors and/or Monte Carlo analysis.

In the case of finite Q simulation, inductors are modeled as an ideal inductor \(L\) with a small resistor \(r\) in series: Inductor Equivalent Circuit The resistnace \(r\) is given by $$r = \frac{2 \pi f_{Q} L}{Q}$$ where \(Q\) in the inductor quality factor and \(f_{Q}\) in the frequency \(Q\) is specified at.

When Monte Carlo analysis in enabled, the simulation is repeated with randomly varing components values. These values are taken to be uniformly distributed within the nominal value +/- the tolerances stated in the export dialog.

4.1.2 LTSpice Examples

Simulating S-parameters, input and output impedance, and group delay

1. Set the following options in the export dialog and click Export.

LTSpice Export Settings

2. Open the circuit file in LTSpice.

LTSpice Schematics

3. Run the simulation by clicking Simulate/Run.

4. To plot the insertion loss, insertion phase, and return loss, click on Settings/Add Traces (or CTRL-A) and select S21(v1) and S11(v1).

LTSpice Plot 1

5. To plot the filter input and output impedance, click on Settings/Add Traces (or CTRL-A) and select Zin(v1) and Zout(v1).

LTSpice Plot 2

6. To plot the group delay, click on Settings/Add Traces (or CTRL-A) and select S21(v1). Then right click on the right vertical axis and select the Group Delay representation.

LTSpice Plot 3

Simulating S-parameters with finite inductor Q

1. Check the finite-Q checkbox in the export dialog, then set the inductors Q value and frequency. Click Export.

LTSpice Export Settings

2. Open the circuit file in LTSpice.

LTSpice Schematics

3. Run the simulation by clicking Simulate/Run.

4. To plot the insertion loss and return loss, click on Settings/Add Traces (or CTRL-A) and select S21(v1) and S11(v1).

LTSpice Plot 1

Simulating S-parameters with Monte Carlo analysis

1. Check the Monte Carlo checkbox in the export dialog, then set the components tolerances. Click Export.

LTSpice Export Settings

2. Open the circuit file in LTSpice.

LTSpice Schematics

3. Run the simulation by clicking Simulate/Run.

4. To plot the insertion, click on Settings/Add Traces (or CTRL-A) and select S21(v1).

LTSpice Plot 1

Simulating transient step and impulse response

1. Set the following options in the export dialog and click Export.

LTSpice Export Settings

2. Open the circuit file in LTSpice.

LTSpice Schematics

3. Run the simulation by clicking Simulate/Run.

4. To plot the step response, click on Settings/Add Traces (or CTRL-A) and select V(vout).

LTSpice Plot 1

4. To plot the impulse response, click on Settings/Add Traces (or CTRL-A) and enter D(V(vout)).

LTSpice Plot 2

4.2 Qucs

Qucs is an open-source circuit simulation software. It runs natively on Windows, Linux and macOS. The latest version is available for download on qucs.sourceforge.net.

4.2.1 Qucs Simulation Settings

The export dialog will create an Qucs .sch file which includes the filter schematics as well as auto-generated simulation settings. The user can select the type of simulation to preform, either being S-parameters or transient response.

4.2.2 Qucs Examples

Simulating S-parameters and group delay

1. Set the following options in the export dialog and click Export.

Qucs Export Settings

2. Open the circuit file in Qucs.

Qucs Schematics

3. Run the simulation by clicking Simulation/Simulate (or F2).

4. To plot the insertion loss and return loss, add a Cartesian diagram from the componenets library and select dBS21 and dBS11.

5. To plot the group delay, add another Cartesian diagram and select group_delay.

Qucs Plot

Simulating transient step and impulse response

1. Set the following options in the export dialog and click Export.

Qucs Export Settings

2. Open the circuit file in Qucs.

Qucs Schematics

3. Run the simulation by clicking Simulation/Simulate (or F2).

4. To plot the step response, add a Cartesian diagram from the componenets library and select Vstep.Vt.

5. To plot the impulse response, add another Cartesian diagram and select Vimpulse.

Qucs Plot


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